1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a data transfer circuit which may be used in a semiconductor apparatus.
2. Related Art
FIGS. 1 and 2 are circuit diagrams of exemplary data transfer circuits of a conventional semiconductor apparatus. Specifically, FIG. 1 is a diagram illustrating a data transfer circuit 1 of a semiconductor apparatus using a conventional switch control scheme, which may include a bit line sense amplifier 10, column switches M1 and M2, and input/output switches M3 and M4.
The column switches M1 and M2 may be coupled between bit lines BLT and BLB and first data lines SIOT and SIOB, respectively.
The input/output switches M3 and M4 may be coupled between the first data lines SIOT and SIOB and second data lines LIOT and LIOB, respectively.
The bit line sense amplifier 10 may be coupled to the bit lines BLT and BLB, and may detect and amplify data on the bit lines BLT and BLB, and output the amplified data to the column switches M1 and M2.
The column switches M1 and M2 may couple the bit lines BLT and BLB to the first data lines SIOT and SIOB, respectively, in response to a column selection signal YI.
The input/output switches M3 and M4 may couple the first data lines SIOT and SIOB to the second data lines LIOT and LIOB, respectively, in response to an input/output control signal IOSW.
In this configuration, the loads of the second data lines LIOT and LIOB may be larger than those of the bit lines BLT and BLB and the first data lines SIOT and SIOB.
Data on the first data lines SIOT and SIOB and data on the second data lines LIOT and LIOB may be driven by a core voltage VCORE with a level corresponding to a half of that of a supply voltage VDD.
One method to transfer data with the level of the core voltage VCORE to the second data lines LIOT and LIOB having a relatively large load without loss, is to apply the input/output control signal IOSW with a level which is equal to or higher than the sum of the threshold voltage of NMOS transistors constituting the input/output switches M3 and M4 and the core voltage VCORE.
Accordingly, a boosting voltage VPP obtained by boosting the supply voltage VDD may be used as the input/output control signal IOSW.
According to some aspects of the conventional art as described above, when detecting the data on the second data lines LIOT and LIOB by a charge sharing operation, the voltage difference between the second data lines LIOT and LIOB, or a delta voltage, is required.
One way to quickly ensure the delta voltage, is to quickly drive the column switches M1 and M2, that is, to advance the activation timing of the column selection signal YI.
FIG. 2 is an illustration of a data transfer circuit 2 using a conventional local amplification scheme which further includes a local sense amplifier.
The local sense amplifier 20 may include a plurality of transistors M5 to M9 which are provided between the first data lines SIOT and SIOB.
The local sense amplifier 20 amplifies the data on the first data lines SIOT and SIOB in response to signals such as an enable signal LSAEN and transfers the amplified data to the second data lines LIOT and LIOB.
One problem with the conventional art is that, since the data transfer circuit 1 using the conventional switch control scheme delays tRCD (RAS to CAS delay) of asynchronous parameters, a tRCD margin is reduced.
Furthermore, in the data transfer circuit depicted in FIG. 2 using the conventional local amplification scheme, the data on the data lines LIOT and LIOB has a relatively large level difference according to the amplification operation of the local sense amplifier 20, as compared with the charge sharing scheme of FIG. 1. Therefore, in a subsequent precharge operation, the consumption of a current for returning the data lines LIOT and LIOB to the level of the core voltage VCORE is increased.